Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits

Authors

  • A. Nabil
  • J. Bernardo
  • A. Rangel
  • M. Shaker
  • M. Abouelatta
  • L. Fakri-Bouchet
  • C. Gontrand

DOI:

https://doi.org/10.14738/tnc.93.10196

Keywords:

Substrate, Interconnects, Electronic noise, via, stress, 3D RF ICs, Green kernel, TLM, Energy Transfer, transfer impedance.

Abstract

3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data.  If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise   between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique.  With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine  where the energy is  really confined in such 3D circuits, before find solutions to limit  pollutions  coming from  electro-magneto -thermal   phenomena or  background noises.

References

N.K. Verghese, D.J. Allstot, and M.A. Wolve, (1995). Fast Parasitic Extraction for Substrate Coupling in Mixed-Signal ICs. Presented at IEEE 1995 CUSTOM INTEGRATED CIRCUITS CONFERENCE

A. Torabian, and Y. L. Chow, “Simulated Image Method for Green’s Function of Multilayer Media” IEEE Transactions On Microwave Theory And Techniques, Vol. 47, No. 9, September 1999.

Chew, Weng Cho,"Waves and fields in inhomogeneous media", IEEE press, 1995.

Chew, Tong, and Hu, "Integral Equations Methods for Electromagnetic and Elastic Waves", Morgan & Claypool, 2008.

A Todri-Sanial, CS Tan, “Physical Design for 3D Integrated Circuits” ,CRC Press, 2017/12/19

R. Gharpurey, and S. Hosur, (1997). Transform Domain Techniques for Efficient Extraction of Substrate Parasitics. Published in: 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A. Samavedam, A. Sadate, K. Mayaram, and and T. S. Fiez, “A Scalable Substrate Noise Coupling Model for Design of Mixed-Signal IC’s” IEEE Journal Of Solid-State Circuits, Vol. 35, No. 6, June 2000.

COMSOL https://www.comsol.com/comsol-multiphysics

MATLAB https://www.mathworks.com/products/matlab.html

C. Torregiani, H. Oprins, B. Vandevelde, E. Beyne, and I. De Wolf, (2009). Compact Thermal Modeling of Hot Spots in Advanced 3D-Stacked ICs. Presented at 11th Electronics Packaging Technology Conference

K. R. Bagnall, Y. S. Muzychka, and E. N. Wang, “Analytical Solution for Temperature Rise in Complex Multilayer Structures With Discrete Heat Sources” IEEE Transactions On Components, Packaging And Manufacturing Technology, Vol. 4, No. 5, May 2014

Y. S. Muzychka, K. R. Bagnall, and E. N. Wang, “Thermal Spreading Resistance and Heat Source Temperature in Compound Orthotropic Systems With Interfacial Resistance” IEEE Transactions On Components, Packaging And Manufacturing Technology, Vol. 3, No. 11, November 2013.

Y. Ma, L. F. Bouchet, F. Calmon, and C. Gontrand, “Electrothermal Modeling for 3-D Nanoscale Circuit Substrates: Noise” IEEE Transactions On Components, Packaging And Manufacturing Technology, Vol. 6, No. 7, July 2016

V. d. Ziel, A. (1970). Noise. Sources, characterization, measurement. . Prentice-Hall Information and System Sciences Series, Englewood Cliffs: Prentice-Hall, 1970

K. M. V. Vliet, A. Friedmann, R. J. J. Zijlstra, A. Gisolf, and A. Ziel, “Noise in single injection diodes. I. A survey of methods” Journal of Applied Physics. Vol. 46. No.4. April 1975.

M. Abouelatta, R. Dahmani, O. Valorge, F. Calmon, and C. Gontrand, “Modelling of through silicon via and devices electromagnetic coupling” Microelectronics Journal, Vol. 42, No. 2, 2011.

R. Weerasekera, D. Pamunuwa, M. Grange, H Tenhunen, and L. R. Zheng, (2009). Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits. Presented at Proceedings of the workshop on 3-D Integration, Design, Automation, and Test in Europe (DATE) Conference.

L. Cadix et al., “RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking”, Microelectronic Engineering. Vol. 87. 2010.

I. Savidis and E. G. Friedman, “Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance” IEEE Transactions On Electron Devices, Vol. 56, No. 9, September 2009.

Nabors, Keith, and Jacob White. "FastCap: A multipole accelerated 3-D capacitance extraction program." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10.11 (1991): 1447-145

Y. MA, et al., “Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method“ Transactions on Networks and Communications, Vol. 7, No. 6, 2019.

S. K. Ryu, K. H. Lu, X. Zhang, J. H. Im, P. S. Ho, and R. Huang, “Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects” IEEE Transactions On Device And Materials Reliability, Vol. 11, No. 1, March 2011.

A. Heryanto, et al., “Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication” Journal of Electronic Materials, Vol. 41, No. 9, 2012. [25] F. C. Nix, and D. Macnair, “The Thermal Expansion of Pure Metals: Copper, Gold, Aluminum, Nickel, and Iron” PH YSI CAL REVIEW, Vol. 60, 1941. [26] A. P. Karmarkar, et al., “Performance and Reliability Impact of Copper Plasticity in Backside TSV-last Fabrication Process” IEEE Transactions on Device and Materials Reliability, Vol. 16, No.3, 2016. [27] A. Nabil , J. Bernardo, Y. Ma, A. Shaker, M. Abouelatta, H. Ragai, and C. Gontrand,” Electrical modeling of tapered TSV including MOS-Field effect and substrate parasitics: Analysis and application” Microelectronics Journal, Vol. 100, 2020. [28] “Sentaurus Process User Guide”, SYNOPSYS, Version H-2013.03, March 2013.

Downloads

Published

2021-05-28

How to Cite

Nabil, A., Bernardo, J., Rangel, A., Shaker, M., Abouelatta, M., Fakri-Bouchet , L., & Gontrand, C. (2021). Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits. Discoveries in Agriculture and Food Sciences, 9(3), 36–54. https://doi.org/10.14738/tnc.93.10196